As shown in FIG. 1, a typical computer system 10 includes at least a microprocessor 12 (often referred to and known as xe2x80x9cCPUxe2x80x9d) and some form of memory 14. The microprocessor 12 has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system 10. Specifically, FIG. 1 shows the computer system 10 having the microprocessor 12, memory 14, integrated circuits (ICs) 16 that have various functionalities, and communication paths 19, i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system 10.
In order to keep pace with improving technologies, computer system and circuit designers are constantly trying to improve and get the most out of their designs through the most cost-effective means. As faster versions of a particular CPU become available, a designer will often try to improve the throughput of their existing design by simply increasing the CPU clock frequency. However, after a certain point, the speed of the system""s main memory becomes a limiting factor in optimizing the throughput of the system. To this end, designers have produced faster memories, which, in turn, has necessitated high-speed memory interfaces.
One type of design that has been used for high-speed memory interface applications involves the use of stub series termination logic (SSTL). SSTL is a standard created by the Joint Electron Device Engineering Council (JEDEC) to provide a termination scheme for high speed signaling in applications such as DDR-SDRAM. SSTL specifies particular switching characteristics such that high operating frequencies are available. As operating frequencies continue to increase and as the demand for faster memory interfaces has and continues to grow, the STTL interface standard continues to enjoy wide acceptance.
According to one aspect of the present invention, an integrated circuit comprises: a biasing circuit arranged to generate a bias signal; a voltage regulator arranged to receive the bias signal and generate a regulated voltage on a terminal thereof; and a voltage translator stage, operatively connected to the terminal, arranged to output a voltage dependent on an input thereto, where the regulated voltage is arranged to serve as a power supply for the voltage translator stage, and where the regulated voltage is less than a power supply voltage of the voltage regulator.
According to another aspect, an integrated circuit comprises: means for generating a bias signal; means for generating a regulated voltage dependent on the bias signal; and means for outputting a signal dependent on an input to the means for outputting the signal, where the means for outputting the signal is dependent on the regulated voltage, and where a maximum voltage of the signal is less than a supply voltage of the means for generating the regulated voltage.
According to another aspect, a method for performing a stub series termination logic operation comprises: generating a bias signal dependent on a power supply voltage; generating a regulated voltage dependent on the bias signal and the power supply voltage; and generating an output signal dependent on an input signal, where the generating the output signal is dependent on the regulated voltage, and where the regulated voltage is less than the power supply voltage.
According to another aspect, an integrated circuit having a core and a memory comprises stub series termination logic circuitry interfaced between the core and the memory, where the stub series termination logic circuitry is arranged to operate off of a power supply voltage, and where the stub series termination logic circuitry comprises: a pre-driver stage arranged to receive an input signal from the core, where the pre-driver stage includes a voltage regulator arranged to operate off of the power supply voltage and generate a regulated voltage on a terminal thereof and a voltage translator stage, operatively connected to the terminal, arranged to output an output signal dependent on the input signal and the regulated voltage; and an output buffer stage arranged to receive and buffer the output signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.